The present invention relates to a semiconductor chip, a method for manufacturing the same, and a stack package using the same, and more particularly, to a semiconductor chip with conductive diffusions regions, a method for manufacturing the same, and a stack package using the same.
In the semiconductor industry, packaging technologies for semiconductor integrated circuits have continuously been developed to meet the demands toward miniaturization and mounting efficiency. Recently, various stacking techniques have been developed. The term “stack” in the semiconductor industry means to vertically place at least two semiconductor chips or semiconductor packages. By using the stacking techniques, it is possible to realize a product having memory capacity at least two times greater than that obtainable through semiconductor integration processes, and mounting area utilization efficiency can be elevated.
In a conventional stack package, through vias may be used to electrically connect one chip to another in the stack. The through vias are formed in such a manner that via holes are defined by etching respective semiconductor chips and a barrier layer and a conductive layer are filled in the via holes.
However, in conventional art, a dry reactive ion etching (DRIE) process may be used to form the via holes in the respective semiconductor chips. Due to this fact, since a separate DRIE equipment for conducting the DRIE process is needed, additional manufacturing processes and costs are required. Additionally, the DRIE process may affect the structure of the semiconductor chip that may lead to failures in the chip.
Also, in the conventional art mentioned above, a number of other equipments, such as a CVD (chemical vapor deposition) equipment for depositing an insulation material in the via holes, a PVD (physical vapor deposition) equipment for forming the barrier layer, a plating equipment for filling the via holes with a conductive material, and so on, may also be needed. As a consequence, in the conventional art, a number of additional equipments may be needed and a lot of costs are incurred to form the through vias in the semiconductor chips, but also a lengthy period may be required to conduct various processes with the respective equipments.